A Logic - Level Model for - Particle Hits in CMOS

Systems designed for reliability must be validated through simulations. However, traditional SPICE like simulators or even mixed-mode simulators are too slow for the task of simulating the eeects of-particle hits on relatively large circuits. Gate-level simulators ooer tremendous speedup over these electrical level simu-lators, but they are only as good as the model which captures the-particle eeect at the logic level. The goal of this research is to develop a computationally eecient model which captures the behavior of the-particle at the logic level. This model can then be used in a gate-level timing simulator to propagate the-particle eeects to the latches and the outputs of the circuit under simulation. We have developed a closed form solution to approximate the logic pulse waveform resulting from-particle hits. As is presented in the paper, the model tracks the data from SPICE simulations remarkably well.